Title :
A 180 MHz multiple-registered DRAM for low-cost 2 MB/chip secondary cache
Author :
Iwamoto, Hisashi ; Watanabe, Naoya ; Yamazaki, Akira ; Sawada, Seiji ; Murai, Yasumitsu ; Konishi, Yasuhiro ; Itoh, Hiroshi ; Miyamoto, Takayuki ; Kumanoya, Masaki
Author_Institution :
ULSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
A Multiple-registered DRAM is described for 2 MB/chip secondary cache. 64 registers per bank of the RAM enable the data transfer from 64 dynamic memory cells to the registers simultaneously, realizing 180 MHz cache fill operation. The area increase with the architecture is only 5.4% over the conventional DRAM, which contributes to realize low-cost high-performance cache systems
Keywords :
DRAM chips; cache storage; memory architecture; 180 MHz; 2 MB; area increase; cache fill operation; data transfer; dynamic memory cells; high-performance cache systems; multiple-registered DRAM; secondary cache; Clocks; Data engineering; Decoding; Delay; Laboratories; Pipelines; Random access memory; Read-write memory; Registers; Timing;
Conference_Titel :
Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-1886-2
DOI :
10.1109/CICC.1994.379653
