Title :
Embedded memory design for a four issue superscaler RISC microprocessor
Author :
Takayanagi, Toshinari ; Sawada, Kazuhiro ; Sakurai, Takayasu ; Parameswar, Yukiko ; Tanaka, Shigeru ; Ikumi, Nobuyuki ; Nagamatsu, Masato ; Kondo, Yoshihisa ; Minagawa, Kenji ; Brennan, John ; Hsu, Peter ; Rodman, Paul ; Bratt, Joe ; Scanlon, Joe ; Tang,
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
Design of embedded memories for a 64 bit superscaler RISC microprocessor is described. Since the microprocessor issues four instructions per cycle including two memory operations at a time, very wide bandwidth of the primary caches (2.4 GB/sec) is vital. The chip includes 16 KB instruction cache, 2 KB branch cache, 16 KB dual ported data cache and 384 entry dual ported TLB. Unique scheme of TLB hit check greatly reduces critical path. The chip is fabricated in Toshiba´s high-speed 0.8 μm CMOS technology utilizing triple metal and triple well. The die size is 17.3 mm×17.3 mm and contains 2.6 million transistors. The chip achieves 75 MHz at 70°C and 3.1 V
Keywords :
CMOS digital integrated circuits; cache storage; microprocessor chips; real-time systems; reduced instruction set computing; 0.8 micron; 16 KB; 2 KB; 2.4 GB/s; 3.1 V; 64 bit; 70 degC; 75 MHz; CMOS technology; branch cache; die size; dual ported TLB; dual ported data cache; embedded memory design; instruction cache; memory operations; primary caches; superscaler RISC microprocessor; triple metal; triple well; Bandwidth; CMOS technology; Computer graphics; Costs; Microprocessors; Pipelines; Random access memory; Read-write memory; Reduced instruction set computing; Silicon;
Conference_Titel :
Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-1886-2
DOI :
10.1109/CICC.1994.379654
