DocumentCode
2488733
Title
An efficient compiled simulation system for VLIW code verification
Author
Ahn, Jae-Woo ; Moon, Soo-Mook ; Sung, Wonyong
Author_Institution
Dept. of Electr. Eng., Seoul Nat. Univ., South Korea
fYear
1998
fDate
5-9 Apr 1998
Firstpage
91
Lastpage
95
Abstract
We present an efficient compiled simulation system for the verification of a VLIW instruction set architecture and its assembly code. Our existing compiled simulation system is made to be faster by adopting incremental recompilation and C-assembly cosimulation techniques to improve the conventional compiled simulation. As a part of SPARC-based VLIW testbed, the efficiency and validity of our compiled simulation system are verified with three SPEC ´89 integer benchmarks and several UNIX utilities
Keywords
digital simulation; instruction sets; parallel architectures; performance evaluation; C-assembly cosimulation; SPEC ´89 integer benchmarks; UNIX utilities; VLIW code verification; assembly code; compiled simulation system; incremental recompilation; instruction set architecture; Assembly systems; Benchmark testing; Hardware; Instruction sets; Moon; Optimizing compilers; Process design; Software performance; System testing; VLIW;
fLanguage
English
Publisher
ieee
Conference_Titel
Simulation Symposium, 1998. Proceedings. 31st Annual
Conference_Location
Boston, MA
ISSN
1080-241X
Print_ISBN
0-8186-8418-6
Type
conf
DOI
10.1109/SIMSYM.1998.668452
Filename
668452
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