A 1.5% jitter PLL clock generation system for a 500-MHz RISC processor

Author

Suzuki, Kenji ; Nakayama, Taiki ; Nomura, M. ; Inoue, Takeru ; Abiko, Hiroshi ; Okabe, Kousuke ; Ono, Atsushi ; Yamashima, M. ; Yamada, Hiroyoshi

fYear

1994

fDate

1-4 May 1994

Firstpage

555

Lastpage

558

Abstract

We have developed a clock generation system for RISC processors. The system consists of two parts of a PLL, a frequency multiplier, and a phase aligner. The multiplier can multiply the input clock frequency by 2, 4, and 8, and can accomplish a wide frequency range of output clocks, from 60 MHz to 660 MHz. Jitter is reduced to 1.5% of the output clock period by separating the clock generation system into a frequency multiplier and a phase aligner, and by developing a new differential loop filter with high sensitivity phase detection. The phase aligner reduces clock skew between the processor and peripheral LSIs. The system is fabricated with 0.4-μm CMOS triple-layer Al process technology and operated at 3.3 V

Keywords

CMOS digital integrated circuits; clocks; digital phase locked loops; frequency multipliers; jitter; microprocessor chips; pulse generators; reduced instruction set computing; 0.4 micron; 3.3 V; 500 MHz; 60 to 660 MHz; CMOS triple-layer Al process technology; PLL clock generation system; RISC processor; clock skew; differential loop filter; frequency multiplier; high sensitivity phase detection; input clock frequency; phase aligner; Clocks; Delay; Filters; Frequency locked loops; Jitter; Phase locked loops; Reduced instruction set computing; Signal generators; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Conference_Location

San Diego, CA

Print_ISBN

0-7803-1886-2

Type

conf

DOI

10.1109/CICC.1994.379661

Filename

379661