• DocumentCode
    2488779
  • Title

    Interconnect design using convex optimization

  • Author

    Sancheti, Piyush K. ; Sapatnekar, Sachin S.

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
  • fYear
    1994
  • fDate
    1-4 May 1994
  • Firstpage
    549
  • Lastpage
    552
  • Abstract
    Two wire sizing formulations for optimizing interconnect are presented. The first minimizes the delay under wire width constraints, while the second minimizes the wiring area under delay and width constraints. A convex programming formulation is proposed, and an efficient algorithm is used to perform the optimization. Experimental results show that the first formulation, which has been the prevalent one in the literature, provides bad engineering solutions, and that the second formulation leads to significantly better results
  • Keywords
    circuit layout CAD; circuit optimisation; convex programming; delays; integrated circuit interconnections; integrated circuit layout; minimisation; IC layout design; convex optimization; convex programming; delay constraint; delay minimisation; interconnect design; wire sizing formulations; wire width constraints; wiring area; Capacitance; Delay; Design optimization; Driver circuits; Integrated circuit interconnections; Timing; Wire; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
  • Conference_Location
    San Diego, CA
  • Print_ISBN
    0-7803-1886-2
  • Type

    conf

  • DOI
    10.1109/CICC.1994.379662
  • Filename
    379662