Title :
Transistor size optimization in layout design rule migration
Author :
Kishida, Satoru ; Shibayama, Yasunori ; Tanizaki, Hiroaki ; Hanami, Atsuo ; Ohkura, Isao
Author_Institution :
Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
A new design rule migration system based on a compaction method has been developed. A transistor size optimization method has been employed in the system to achieve high performance of the circuit. The cost functions for the optimization are critical path delay time and power dissipation. The experimental work for a discrete cosign transform core processor (102 transistors) has shown the effectiveness of the migration system and the optimization method
Keywords :
VLSI; circuit layout CAD; circuit optimisation; integrated circuit layout; DCT processor; IC layout; compaction method; cost functions; critical path delay time; layout design rule migration; power dissipation; transistor size optimization; Circuits; Compaction; Design optimization; Discrete transforms; Laboratories; Large scale integration; Optimization methods; Power dissipation; Timing; Transistors;
Conference_Titel :
Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-1886-2
DOI :
10.1109/CICC.1994.379664
