Title :
A 85-mW, 10-bit 40-Ms/s ADC with decimated parallel architecture
Author :
Nakamura, Kentaro ; Hotta, M. ; Carley, R. ; Allstot, D.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
The design of a low-power, 10-bit 40-Ms/s ADC integrated in 0.8-μm multi-threshold CMOS is presented. This fully differential design employs a decimated parallel combination of single-bit and multi-bit per stage pipelined architectures to achieve this performance. The ADC, targeted for high resolution video terminals, dissipates 85-mW from 2.7-V supply, and occupies an area of 1.9 by 2.1-mm2
Keywords :
CMOS integrated circuits; analogue-digital conversion; parallel architectures; pipeline processing; video equipment; video signal processing; 0.8 micron; 10 bit; 2.7 V; 85 mW; ADC; decimated parallel architecture; fully differential design; high resolution video terminals; multi-threshold CMOS; pipelined architectures; Analog-digital conversion; Bandwidth; Circuits; Computer architecture; Interleaved codes; Laboratories; Machine vision; Parallel architectures; Pipeline processing; Power dissipation;
Conference_Titel :
Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-1886-2
DOI :
10.1109/CICC.1994.379675
