Behavioral simulation techniques for phase/delay-locked systems

Author

Demir, Alper ; Liu, Edward ; Sangiovanni-Vincentelli, Alberto L. ; Vassiliou, Iasson

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

1994

fDate

1-4 May 1994

Firstpage

453

Lastpage

456

Abstract

This paper presents behavioral simulation techniques for phase/delay-locked systems. Numerical simulation algorithms are compared and the issue of numerical noise is discussed. Behavioral phase noise simulation for phase/delay-locked systems is described. The role of behavioral simulation for phase/delay-locked systems in our top-down constraint-driven design methodology, and in bottom-up verification of designs, is explained with examples. Accuracy and efficiency comparisons with other methods are made. Simulation techniques are described in the framework of phase/delay-locked systems, but simulation methodology and the results attained in this work are applicable to the behavioral simulation of mixed-mode nonlinear dynamic systems

Keywords

circuit CAD; circuit analysis computing; delay circuits; digital simulation; integrated circuit design; mixed analogue-digital integrated circuits; phase locked loops; PLLs; behavioral simulation techniques; bottom-up verification; delay-locked loops; mixed-mode nonlinear dynamic systems; numerical simulation algorithms; phase/delay-locked systems; simulation methodology; top-down constraint-driven design; Analog circuits; Circuit simulation; Clocks; Computational modeling; Delay systems; Design methodology; Digital circuits; Discrete event simulation; Phase locked loops; Phase noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Conference_Location

San Diego, CA

Print_ISBN

0-7803-1886-2

Type

conf

DOI

10.1109/CICC.1994.379684

Filename

379684