Improved estimation of the switching activity for reliability prediction in VLSI circuits

Estimating the reliability of integrated circuits is a major concern of the semiconductor industry. In CMOS circuits, the extent of node switching activity, called the transition density, is a good measure of susceptibility to a variety of reliability problems. However the density computation algorithm does not take into account the effect of the inertial delay of logic gates. Thus, the transition density may be severely overestimated in high frequency applications. To overcome this problem, we model the effect of gate delay in the form of a conceptual low-pass filter block that does not allow unacceptably short logic pulses to propagate through. Using a stochastic model of logic signals, we then derive the equations required to propagate the transition density through the filter. We will present experimental results that illustrate the validity and importance of these results