Title :
Circuit partitioning for pipelined pseudo-exhaustive testing using simulated annealing
Author :
Liou, Huoy-Yu ; Lin, Ting-Ting Y. ; Liu, Lung-Tien ; Cheng, Chung-Kuan
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
Abstract :
A novel approach for partitioning circuits with high fan-ins which are not suitable for pseudo-exhaustive testing is presented. Circuits under test (CUTs) are modeled as directed graphs and cost function is developed for the optimization algorithm. Disjoint circuit partitions are generated not only for reducing the exhaustive test length but also for pipelined testing. Experiments on benchmark circuits demonstrate that simulated annealing produces good results for future applications
Keywords :
built-in self test; circuit optimisation; combinational circuits; directed graphs; logic partitioning; logic testing; simulated annealing; BIST; benchmark circuits; circuit partitioning; circuits under test; combinational circuits; cost function; directed graphs; disjoint circuit partitions; exhaustive test length; fault coverage; optimization algorithm; pipelined pseudo-exhaustive testing; simulated annealing; testing time; Automatic testing; Benchmark testing; Circuit simulation; Circuit testing; Computational modeling; Cost function; Partitioning algorithms; Registers; Simulated annealing; Timing;
Conference_Titel :
Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-1886-2
DOI :
10.1109/CICC.1994.379690
