Analog testability analysis and fault diagnosis using behavioral modeling

Author

Liu, Edward ; Kao, William ; Felt, Eric ; Sangiovanni-Vincentelli, Alberto

Author_Institution

Cadence Design Syst. Inc., San Jose, CA, USA

fYear

1994

fDate

1-4 May 1994

Firstpage

413

Lastpage

416

Abstract

This paper presents an efficient strategy for testability analysis and fault diagnosis of analog circuits using behavioral models. A key contribution is a new algorithm for determining analog testability. Experimentally, we determined the testability and faults of a fabricated 10 bit digital-to-analog converter modeled using the analog hardware description language, Cadence-AHDL. Also, we applied the testability analysis at the circuit level using SPICE sensitivity analysis

Keywords

SPICE; analogue circuits; circuit testing; digital-analogue conversion; fault diagnosis; hardware description languages; 10 bit; Cadence-AHD; SPICE sensitivity analysis; algorithm; analog circuits; analog hardware description language; analog testability analysis; behavioral modeling; digital-to-analog converter; fault diagnosis; Analog circuits; Circuit analysis; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Digital-analog conversion; Fault diagnosis; Hardware design languages; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Conference_Location

San Diego, CA

Print_ISBN

0-7803-1886-2

Type

conf

DOI

10.1109/CICC.1994.379691

Filename

379691