A Modified CMOS Frequency Doubler Considering Delay Time Matching Condition

In this paper, a frequency doubler is designed that converts from 1.15 GHz input signal to 2.3 GHz output signal using TSMC 0.18 CMOS technology. The proposed doubler consist of a fully adjustable Schmitt trigger (FAST), time-delay components, XOR gate and a voltage controlled delay line (VCDL). Time-delay components use RC integrator and comparator. Advantages of this topology include good fundamental frequency and harmonic frequency suppression, compact layout and low power consumption. The desired signal at 2.3 GHz is 0.871 dBm. The fundamental frequency at 1.15 GHz and third harmonic frequency at 3.45 GHz approximately 37 dBc below the 2.3 GHz signal. The fourth harmonic frequency at 4.6 GHz is approximately 24 dBc below the 2.3 GHz signal. The power consumption is 11.07 mW and the phase noise of the output signal is 100.5 dBc/Hz at 10 KHz offset.