DocumentCode
2489796
Title
Manufacturability analysis environment-MAPEX
Author
Heineken, H.T. ; Maly, W.
Author_Institution
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear
1994
fDate
1-4 May 1994
Firstpage
309
Lastpage
312
Abstract
A CAD manufacturability analysis environment, MAPEX, is described in this paper. It can be used to extract a large number of manufacturability/yield relevant design attributes from an IC layout. The extracted attributes can then be used to improve design tools/strategies or to analyze the reasons for observed yield loss
Keywords
CAD/CAM; design for manufacture; economics; integrated circuit design; integrated circuit yield; CAD manufacturability; IC layout; MAPEX; design strategies; design tools; manufacturability analysis environment; manufacturability parameters extraction environment; yield loss; yield relevant design attributes; Circuit faults; Costs; Design automation; Integrated circuit modeling; Integrated circuit yield; Process design; Pulp manufacturing; Semiconductor device manufacture; Semiconductor device measurement; Virtual manufacturing;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
Conference_Location
San Diego, CA
Print_ISBN
0-7803-1886-2
Type
conf
DOI
10.1109/CICC.1994.379712
Filename
379712
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