DocumentCode
2490136
Title
A programmable digital signal processor for service adaptive access
Author
Mitchler, D. ; Aly, S.
Author_Institution
Bell-Northern Res., Ottawa, Ont., Canada
fYear
1994
fDate
1-4 May 1994
Firstpage
219
Lastpage
222
Abstract
A programmable 24-bit RISC-based Digital Signal Processor with oversampled ADC and DAC has been designed in 1.2 μm CMOS for use in a service adaptive subscriber loop interface. The processor has an instruction rate of 20.48 MHz and can perform most of the signal processing requirements for many services ranging from POTS to ISDN-U
Keywords
CMOS integrated circuits; ISDN; VLSI; analogue-digital conversion; digital filters; digital signal processing chips; digital-analogue conversion; mixed analogue-digital integrated circuits; reduced instruction set computing; subscriber loops; 1.2 micron; 20.48 MHz; 24 bit; CMOS; ISDN-U; POTS; RISC-based DSP; instruction rate; line card; oversampled ADC; oversampled DAC; programmable digital signal processor; service adaptive access; signal processing requirements; subscriber loop interface; Adaptive signal processing; Circuits; Clocks; Computer architecture; Digital signal processing; Digital signal processing chips; Digital signal processors; ISDN; Reduced instruction set computing; Telephony;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
Conference_Location
San Diego, CA
Print_ISBN
0-7803-1886-2
Type
conf
DOI
10.1109/CICC.1994.379732
Filename
379732
Link To Document