Title :
An 180 MHz 16 bit multiplier using asynchronous logic design techniques
Author :
Burford, Richard G. ; Fan, Xingcha ; Bergmann, Neil W.
Author_Institution :
Joint Res. Centre in Inf. Technol., Flinders Univ., Adelaide, SA, Australia
Abstract :
A CMOS digital logic design technique is described which exploits the advantages of fast precharged logic and efficient latch design commonly used in synchronous systems while maintaining the features of localized control inherent in asynchronous design. A pipelined sixteen bit multiplier is presented and its performance compared with several previously reported asynchronous and synchronous designs
Keywords :
CMOS logic circuits; asynchronous circuits; carry logic; logic design; multiplying circuits; pipeline arithmetic; 16 bit; 180 MHz; CMOS digital logic design; asynchronous logic design techniques; fast precharged logic; latch design; multiplier design; pipelined sixteen bit multiplier; Buffer storage; CMOS logic circuits; Clocks; Delay; Digital signal processing chips; Information technology; Inverters; Logic design; Switches; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-1886-2
DOI :
10.1109/CICC.1994.379733
