A novel reprogrammable interconnect architecture with decoded RAM storage

Author

Guo, Richard ; Nguyen, Hung ; Srinivasan, Adi ; Nasir, Quaid ; Cai, Hong ; Law, Steve ; Mohsen, Amr

Author_Institution

Aptix Corp., San Jose, CA, USA

fYear

1994

fDate

1-4 May 1994

Firstpage

193

Lastpage

196

Abstract

Using a new architecture and routing scheme, a second generation 1024 pin interconnect device features up to 40% die size reduction and twice the speed. A novel decoded RAM storage and 5 T RAM cell yield the area reduction. The new architecture also adds 256 buffers. Unbuffered paths are passive and bi-directional. The programming time of on-chip memory also improves dramatically from 40 ms to less than 1 ms

Keywords

CMOS memory circuits; SRAM chips; VLSI; decoding; integrated circuit interconnections; network routing; random-access storage; 1024 pin interconnect device; SRAM; area reduction; bi-directional; buffers; decoded RAM storage; die size reduction; on-chip memory; programming time; reprogrammable interconnect architecture; routing scheme; second generation; unbuffered paths; Bidirectional control; CMOS process; CMOS technology; Decoding; Integrated circuit interconnections; Pins; Random access memory; Read-write memory; Routing; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Conference_Location

San Diego, CA

Print_ISBN

0-7803-1886-2

Type

conf

DOI

10.1109/CICC.1994.379738

Filename

379738

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2490237