Title :
SIPPOS (single poly pure CMOS) EEPROM embedded FPGA by news ring interconnection and highway path
Author :
Ohsaki, Katsuhiko ; Asamoto, N. ; Takaya, Yasuzo
Author_Institution :
Adv. Syst. Dev., IBM Japan Ltd., Tokyo, Japan
Abstract :
A FPGA architecture of two key features is developed. The one is non-volatility with thousands cycles of reprogramming by SIPPOS (single poly pure CMOS) EEPROM which is by standard CMOS process and does not require any additional processing, the other high efficiency of routing/wiring and high speed/low power consumption by a unique hierarchical structure of NEWS (north, east, west, south) ring interconnection and highway path which minimizes number of transfer gates in a path. They are applied to prototype chip design. By this architecture, low cost, non-volatile, high speed and low power FPGA is realized
Keywords :
CMOS integrated circuits; EPROM; field programmable gate arrays; network routing; power consumption; programmable logic arrays; EEPROM; FPGA architecture; SIPPOS; embedded FPGA; field programmable gate array; high efficiency; high speed; highway path; low power consumption; news ring interconnection; non-volatility; prototype chip design; reprogramming; routing; single poly pure CMOS; standard CMOS process; transfer gates; unique hierarchical structure; wiring; CMOS logic circuits; CMOS process; EPROM; Energy consumption; Field programmable gate arrays; Integrated circuit interconnections; Latches; Logic circuits; MOS devices; Road transportation;
Conference_Titel :
Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-1886-2
DOI :
10.1109/CICC.1994.379739
