Title :
A low noise CMOS frequency synthesizer with dynamic bandwidth control
Author :
Bayer, M. ; Chomicz, T. ; James, F. ; McEntarfer, P. ; Mijuskovic, D. ; Porter, J.
Author_Institution :
Semicustom Operation, Motorola Inc., USA
Abstract :
A low noise 0.8 μm CMOS phase locked loop (PLL) with a maximum output frequency of I20 MHz has been developed for a pixel clock generator for a range of computer monitors. Other applications include computer clock generation and disk drives. The synthesizer requires no external components. A low phase noise has been achieved through supply rejection techniques, by placing the oscillator in a high gain feedback loop to minimize its noise contribution, and by dynamically adjusting the PLL bandwidth to maximize the open loop gain
Keywords :
CMOS analogue integrated circuits; circuit feedback; frequency synthesizers; integrated circuit noise; phase locked loops; phase noise; 120 MHz; CMOS frequency synthesizer; PLL bandwidth; computer clock generation; computer monitors; disk drives; dynamic adjustment; dynamic bandwidth control; high gain feedback loop; low noise operation; low phase noise; open loop gain; oscillator; phase locked loop; pixel clock generator; supply rejection techniques; Application software; Bandwidth; Clocks; Computer applications; Computer displays; Disk drives; Frequency synthesizers; Noise generators; Phase locked loops; Phase noise;
Conference_Titel :
Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-1886-2
DOI :
10.1109/CICC.1994.379743
