Title :
Automatic synthesis and the cost of testing
Author :
Marchok, Thomas E. ; Mary, W.
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Abstract :
Retiming has been postulated as an optimization technique which increases performance at the expense of area. This paper shows that a relationship exists between performance and testability. Designers must be aware of this relationship as the blind use of synthesis tools may yield unexpected and dramatic results. This paper demonstrates that retiming can increase the test generation time required to attain a given fault efficiency by more than two orders of magnitude, and cause a considerable decrease in the fault coverage which is attained
Keywords :
circuit CAD; circuit optimisation; fault diagnosis; integrated circuit design; integrated circuit testing; automatic synthesis; fault coverage; fault efficiency; optimization technique; performance; retiming; synthesis tools; test generation time; testability; testing cost; Automatic testing; Circuit faults; Circuit synthesis; Circuit testing; Costs; Delay; Job design; Sequential analysis; Sequential circuits; Space exploration;
Conference_Titel :
Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-1886-2
DOI :
10.1109/CICC.1994.379751
