Title :
A single chip multimedia video processor
Author :
Balmer, K. ; Ing-Simmons, N. ; Moyse, P. ; Robertson, I. ; Keay, J. ; Hammes, M. ; Oakland, E. ; Simpson, R. ; Barr, G. ; Roskell, D.
Author_Institution :
M.O.S. Design Dept., Texas Instrum. Ltd., Bedford, UK
Abstract :
This paper describes the architecture of a “state of the art” scalable DSP processing system on a single chip. The chip is called the Multimedia Video Processor (MVP) and is the performance flagship of the Texas Instruments TMS320 DSP processor family. This chip utilizes an enhanced 0.5 μm triple-level metal 16M DRAM CMOS process. This highly programmable chip, which can sustain over two billion RISC-like operations per second will be used in systems requiring combinations of graphics acceleration, image processing, encoding/decoding compression processing, for example JPEG, MPEG (audio and video), P×64 standards as well as proprietary compression algorithms. The MVP creates a new frontier of applications for DSP processing
Keywords :
CMOS digital integrated circuits; data compression; digital signal processing chips; image coding; image processing equipment; multimedia communication; multimedia computing; parallel architectures; reduced instruction set computing; video equipment; video signal processing; 0.5 micron; JPEG; MPEG; P×64 standards; RISC; TMS320 DSP processor family; Texas Instruments DSP processor family; architecture; compression algorithms; encoding/decoding compression processing; graphics acceleration; image processing; programmable chip; scalable DSP processing system; single chip multimedia video processor; triple-level metal CMOS process; Acceleration; CMOS process; Decoding; Digital signal processing chips; Graphics; Image coding; Image processing; Instruments; Transform coding; Video compression;
Conference_Titel :
Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-1886-2
DOI :
10.1109/CICC.1994.379760
