RRANN: the run-time reconfiguration artificial neural network

Author

Eldredge, James G. ; Hutchings, Brad L.

Author_Institution

Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA

fYear

1994

fDate

1-4 May 1994

Firstpage

77

Lastpage

80

Abstract

Run-time reconfiguration is a way of more fully exploiting the flexibility of reconfigurable field programmable gate arrays (FPGAs). The run-time reconfiguration artificial neural network (RRANN) uses runtime reconfiguration to increase the hardware density of FPGAs. This is done by dividing the backpropagation algorithm into three sequentially executed stages and configuring the FPGAs to execute only one stage at a time. The FPGAs are reconfigured as part of normal execution in order to change stages. Using reconfigurability in this way increases the number of hardware neurons a single FPGA can implement by 500%. The RRANN architecture has been designed and built using commercially available hardware, and its performance has been measured

Keywords

ART neural nets; backpropagation; field programmable gate arrays; programmable logic arrays; reconfigurable architectures; FPGAs; RRANN; backpropagation algorithm; commercially available hardware; hardware density; hardware neurons; reconfigurable field programmable gate arrays; run-time reconfiguration artificial neural network; sequentially executed stages; Artificial neural networks; Backpropagation algorithms; Circuits; Field programmable gate arrays; Neural network hardware; Neural networks; Neurons; Programmable logic arrays; Prototypes; Runtime;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Conference_Location

San Diego, CA

Print_ISBN

0-7803-1886-2

Type

conf

DOI

10.1109/CICC.1994.379763

Filename

379763