Title :
A quick way to find the optimized performance of a power constrained logic circuit
Author :
Lowe, Kerry S. ; Gulak, P. Glenn
Author_Institution :
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Abstract :
Single-independent path (SIP) analysis is a quick and accurate method for estimating the optimized delay of a logic circuit as a function of power constraint. The technique is based on the realization that a certain class of networks, called SIP, can be easily and precisely optimized by analytic means and that other networks can be accurately approximated by a SIP network. SIP analysis optimizes gate sizes and handles both flat and hierarchical networks. Example results confirm the utility of the technique for a diverse range of applications including network selection, data path optimization, and BiCMOS versus CMOS comparison
Keywords :
BiCMOS digital integrated circuits; BiCMOS logic circuits; circuit analysis computing; circuit optimisation; combinational circuits; delays; logic CAD; logic design; logic gates; BiCMOS; CMOS; combinational logic; data path optimization; flat networks; gate sizes; hierarchical networks; network selection; optimized delay; optimized performance; power constrained logic circuit; single-independent path analysis; BiCMOS integrated circuits; Capacitance; Constraint optimization; Delay estimation; Design optimization; Lagrangian functions; Libraries; Logic circuits; Performance analysis; Wire;
Conference_Titel :
Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-1886-2
DOI :
10.1109/CICC.1994.379772
