Title :
An RTL-to-Grid Design Flow for Power Grid Verification Based on a Statistical Estimation Engine
Author :
Karampatzakis, D.P. ; Evmorfopoulos, N.E. ; Tsiampas, M.K. ; Stamoulis, G.I.
Author_Institution :
Dept. of Comput. & Commun. Eng., Thessaly Univ.
Abstract :
The most important reliability problem of modern power distribution networks is the voltage drop or IR-drop problem. In this paper we present a design flow based on industrial tools for power grid verification, where the grid is modeled as a linear resistive network and the necessary maximum current estimates are statistically obtained by recent advances in the field of extreme value theory. Experimental results include the verification of power grid for a choice of different real designs
Keywords :
estimation theory; integrated circuit modelling; linear network synthesis; power supply circuits; statistical analysis; RTL-to-grid design flow; extreme value theory; linear resistive network; power grid verification; statistical estimation engine; Circuit simulation; Computer networks; Engines; Integrated circuit reliability; Logic circuits; Power grids; Power systems; RLC circuits; State estimation; Voltage;
Conference_Titel :
Research in Microelectronics and Electronics 2006, Ph. D.
Conference_Location :
Otranto
Print_ISBN :
1-4244-0157-7
DOI :
10.1109/RME.2006.1689890
