Title :
Evaluation of Hierarchical FPGA partitioning methodologies based on architecture Rent Parameter
Author :
Marrakchi, Zied ; Mrabet, Hayder ; Mehrez, Habib
Author_Institution :
Dept. ASIM-LIP6, Univ. Paris
Abstract :
The complexity of circuits to implement on FPGA has necessitated to explore hierarchical interconnect architectures. A large body of work shows that a good partitioning hierarchy, as measured by the associated rent parameter, will correspond to an area-efficient layout. We define the architecture rent parameter of a netlist to be the lowest bound on the rent parameter of any partitioning hierarchy of the netlist. Experimental results show that a combination between a multilevel bottom-up clustering and a top-down refinement generates partitioning hierarchies whose rent parameters are lower than those of other methods
Keywords :
field programmable gate arrays; logic partitioning; architecture rent parameter; hierarchical FPGA partitioning; hierarchical interconnect architectures; multilevel bottom-up clustering; partitioning hierarchy; Area measurement; Convergence; Field programmable gate arrays; Integrated circuit interconnections; Programmable logic arrays; Refining; Routing; Switches; Topology; Wiring;
Conference_Titel :
Research in Microelectronics and Electronics 2006, Ph. D.
Conference_Location :
Otranto
Print_ISBN :
1-4244-0157-7
DOI :
10.1109/RME.2006.1689902