Reversed Double Pole-Zero Cancellation Frequency Compensation Technique for Three-Stage Amplifiers

Author

Grasso, A.D. ; Marano, D. ; Palumbo, G. ; Pennisi, S.

Author_Institution

Dipt. di Ingegneria Elettrica Elettronica e dei Sistemi, Catania Univ.

fYear

0

fDate

0-0 0

Firstpage

153

Lastpage

156

Abstract

A novel frequency compensation technique for three-stage amplifiers is introduced. The proposed solution exploits two Miller capacitors, two resistors and an additional feedforward stage which can be implemented without entailing extra transistors. Design equations using the phase margin as design parameter are carried out. The technique is used to design, with a standard CMOS 0.35-mum process, a 2-V three-stage amplifier driving a 500-pF load capacitor. The amplifier dissipates only 70muA at DC and achieves a 1.2-MHz gain-bandwidth product, showing a significant improvement in (MHz-pF)/mA performance

Keywords

capacitors; feedforward amplifiers; integrated circuit design; operational amplifiers; poles and zeros; resistors; 0.35 micron; 1.2 MHz; 2 V; 500 pF; 70 muA; CMOS process; Miller capacitors; feedforward stage; frequency compensation; load capacitor; pole-zero cancellation; resistors; three-stage amplifiers; Bandwidth; Capacitors; Equations; Frequency; Poles and zeros; Resistors; Stability; Topology; Transconductance; Transfer functions;

fLanguage

English

Publisher

ieee

Conference_Titel

Research in Microelectronics and Electronics 2006, Ph. D.

Conference_Location

Otranto

Print_ISBN

1-4244-0157-7

Type

conf

DOI

10.1109/RME.2006.1689919

Filename

1689919