Hardware synthesis from SPDF representation for multimedia applications

Even though high-level hardware synthesis from dataflow graphs is becoming popular in designing DSP (digital signal processor) systems, the currently used dataflow models are inefficient for dealing with the emerging multimedia applications, since they do not support global parameter updates. In this paper, we propose a VHDL code generation method from synchronous piggybacked dataflow (SPDF), which is an extension of synchronous dataflow (SDF), for representing multimedia applications. By constructing a globally shared memory structure with limited access, we can obtain a more efficient RTL (register transfer level) architecture, in terms of memory and performance, compared with other approaches. We demonstrate the usefulness of the proposed approach using a preliminary example of MP3 decoders