Bit-Line Organization in Register Files for Low-Power and High-Performance Applications

Author

Patwary, Ataur R. ; Greub, Hans ; Wang, Zhongfeng ; Geuskens, Bibiche M.

Author_Institution

Intel Corp., Hillsboro, OR

fYear

2006

fDate

19-21 Dec. 2006

Firstpage

505

Lastpage

508

Abstract

As the leakage current keeps increasing in every generation of VLSI processing technology, appropriate selection of the local and global bit-line organization of Register Files (RFs) becomes an important design issue for low-power and high-performance applications. In this paper, several different bit-line organizations are proposed based on simulation results for designing low-power and high-performance RFs using 65 nm CMOS devices, while maintaining maximum robustness against noise.

Keywords

CMOS integrated circuits; integrated circuit design; low-power electronics; radiofrequency integrated circuits; 65 nm; CMOS devices; RF; bit-line organization; high performance applications; low power applications; register files; Application software; Design engineering; Electronic mail; Energy consumption; Leakage current; MOS devices; Radio frequency; Registers; Threshold voltage; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2006. ICECE '06. International Conference on

Conference_Location

Dhaka

Print_ISBN

98432-3814-1

Type

conf

DOI

10.1109/ICECE.2006.355679

Filename

4178515

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2491943