Inter-Processor Communication Performance of a Hierarchical Torus Network under Bit-Flip Traffic Patterns

Author

Rahman, M. M Hafizur ; Ghosh, Manas ; Horiguchi, Susumu

Author_Institution

Dept. of Comput. Sci. & Eng., KUET, Khulna

fYear

2006

fDate

19-21 Dec. 2006

Firstpage

573

Lastpage

576

Abstract

In this paper, we present a deadlock-free routing algorithm for the hierarchical torus network (HTN) using 2 virtual channels - 2 being the minimum number for dimension order routing - and evaluate the network´s inter-processor communication performance under the bit-flip traffic pattern using the proposed routing algorithm. We evaluate the inter-processor communication performance of HTN, H3D-mesh, TESH, mesh, and torus network by computer simulation. It is shown that the inter-processor communication performance of the HTN is better than that of the H3D-mesh, TESH, mesh, and torus networks.

Keywords

multiprocessor interconnection networks; network routing; parallel machines; H3D-mesh; HTN; TESH; bit-flip traffic patterns; computer simulation; deadlock-free routing; dimension order routing; hierarchical torus network; inter-processor communication; Computer networks; Computer simulation; Concurrent computing; Hardware; Mesh networks; Multiprocessor interconnection networks; Routing; System recovery; Telecommunication traffic; Traffic control; HTN; bit-flip traffic pattern; deadlock-free routing; inter-processor communication performance;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2006. ICECE '06. International Conference on

Conference_Location

Dhaka

Print_ISBN

98432-3814-1

Type

conf

DOI

10.1109/ICECE.2006.355696

Filename

4178532