DocumentCode
2492439
Title
A Low power and highly parallel implementation of the H.264 8 × 8 transform and quantization
Author
Elhaji, Majdi ; Zitouni, Abdlekrim ; Meftali, Samy ; Dekeyser, Jean-Luc ; Tourki, Rached
Author_Institution
Lab. of Electron. & Micro-Electron. (Lab.-IT06), Monastir, Tunisia
fYear
2010
fDate
15-18 Dec. 2010
Firstpage
528
Lastpage
531
Abstract
With the appearance of new video standards like H.264/AVC, demands of real-time encoding are increasing. Real-time is a main necessity for video compression and transmission. Discrete Cosine Transform (DCT) and quantization in H.264 have an important role to express real-time. Nevertheless, for real time operation, parallel processing is the most powerful approach that can be used to give considerable compression performance at standard definition (SD) and high definition (HD) resolution. In this paper a highly parallel hardware implementation of the H.264 8×8 integer transformation and quantization is presented. Experiment results show that this architecture satisfies the real-time constraints intended by different video mobile application.
Keywords
discrete cosine transforms; high definition video; image resolution; low-power electronics; parallel processing; quantisation (signal); video coding; DCT; H.264 integer transformation; H.264/AVC standard; discrete cosine transform; high definition resolution; low power implementation; parallel processing; quantization; real-time encoding; standard definition resolution; video compression; video standards; video transmission; Automatic voltage control; Clocks; Computer architecture; Discrete cosine transforms; Quantization; Real time systems; DCT; H.264; Real-time; parallelism;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing and Information Technology (ISSPIT), 2010 IEEE International Symposium on
Conference_Location
Luxor
Print_ISBN
978-1-4244-9992-2
Type
conf
DOI
10.1109/ISSPIT.2010.5711774
Filename
5711774
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