Title :
Efficient partitioning method for distributed logic simulation of VLSI circuits
Author :
Guettaf, A. ; Bazargan-Sabet, P.
Author_Institution :
Univ. Pierre et Marie Curie, Paris, France
Abstract :
Distributed simulation is expected to provide a significant speed up of simulation run time. Partitioning and load balancing are very influential factors for speed up. The paper presents an efficient partitioning method for distributed VLSI circuits simulation. The main features of this method are the use of a logic replication algorithm. A realistic cost function based on precalculated activity of the circuit using a probabilistic algorithm, and a the balance between execution cost and communication cost. A distributed simulator based on a conservative synchronization method has been used to evaluate the performance of the partitioning
Keywords :
VLSI; circuit analysis computing; distributed algorithms; logic CAD; logic partitioning; resource allocation; synchronisation; VLSI circuits; communication cost; conservative synchronization method; distributed logic simulation; distributed simulator; efficient partitioning method; execution cost; load balancing; logic replication algorithm; performance evaluation; precalculated activity; probabilistic algorithm; realistic cost function; simulation run time speed up; Circuit simulation; Clustering algorithms; Computational modeling; Cost function; Discrete event simulation; Load management; Logic circuits; Partitioning algorithms; Very large scale integration; Workstations;
Conference_Titel :
Simulation Symposium, 1998. Proceedings. 31st Annual
Conference_Location :
Boston, MA
Print_ISBN :
0-8186-8418-6
DOI :
10.1109/SIMSYM.1998.668488
