• DocumentCode
    2492578
  • Title

    DAC nonlinearity and residue gain error correction in a pipelined ADC using a split-ADC architecture

  • Author

    Ahmed, Imran ; Johns, David A.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Toronto Univ., Ont.
  • fYear
    0
  • fDate
    0-0 0
  • Firstpage
    289
  • Lastpage
    292
  • Abstract
    A split-ADC architecture is used to calibrate both the non-linearity errors introduced by capacitor mismatches in the DAC, and gain errors in the residue amplifier of the first stage in a pipelined ADC. The background scheme only requires 105 clock cycles to perform the calibration to more than 12b accuracy. Simulated in Simulink and Spice, the digital calibration scheme improves the ADC´s SNDR/SFDR from 54dB/58dB before calibration to 78dB/85dB after calibration
  • Keywords
    analogue-digital conversion; calibration; digital-analogue conversion; pipeline processing; DAC nonlinearity correction; capacitor mismatch; digital calibration; pipelined ADC; residue amplifier; residue gain error correction; split-ADC architecture; CMOS technology; Calibration; Clocks; Computer architecture; Computer errors; Costs; Energy consumption; Error correction; MIM capacitors; Pipelines;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Research in Microelectronics and Electronics 2006, Ph. D.
  • Conference_Location
    Otranto
  • Print_ISBN
    1-4244-0157-7
  • Type

    conf

  • DOI
    10.1109/RME.2006.1689953
  • Filename
    1689953
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2492578