ESD Protection Design for CMOS Integrated Circuits with Mixed-Voltage I/O Interfaces

Author

Chang, Wei-Jen ; Ker, Ming-Dou

Author_Institution

Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu

fYear

0

fDate

0-0 0

Firstpage

305

Lastpage

308

Abstract

With consideration on the gate-oxide reliability, the new ESD protection design with ESD bus for 1.2/2.5-V mixed-voltage I/O interfaces is reported by using the new proposed high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit. This proposed power-rail ESD clamp circuit with only 1.2-V low-voltage NMOS/PMOS devices can be operated under the 2.5-V input conditions without suffering the gate-oxide reliability issue. The experimental results in a 0.13-mum CMOS process have confirmed that the proposed power-rail ESD clamp circuit has high human-body-model (HBM) and machine-model (MM) ESD robustness and fast turn-on speed. The proposed power-rail ESD clamp circuit is an excellent ESD protection solution to the mixed-voltage I/O interfaces

Keywords

CMOS integrated circuits; electrostatic discharge; integrated circuit reliability; mixed analogue-digital integrated circuits; 0.13 micron; 1.2 V; 2.5 V; CMOS integrated circuits; ESD protection design; NMOS device; PMOS devices; clamp circuit; gate-oxide reliability; human-body-model; machine-model; mixed-voltage I/O interfaces; power-rail electrostatic discharge; CMOS integrated circuits; Clamps; Diodes; Electrostatic discharge; MOS devices; Power supplies; Protection; Stress; Variable structure systems; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Research in Microelectronics and Electronics 2006, Ph. D.

Conference_Location

Otranto

Print_ISBN

1-4244-0157-7

Type

conf

DOI

10.1109/RME.2006.1689957

Filename

1689957