FPGA based design and implementation of an Adaptive Binary Integrator

Binary detection integrator is characterized by its simplicity, resistance against asynchronous interference, and its good detection performance. It suffers from detection loss due to non-homogeneous background. To overcome the limitations of binary integration, the Adaptive Binary Integrator (ABI) is used. ABI achieves the advantages of automatic detection and adaptive thresholding over the binary integrator. The presented adaptive binary integrator is designed and implemented using field programmable gate arrays (FPGAs). The performance of the proposed ABI is evaluated through the Receiver Operating Characteristic (ROC). The implemented hardware is evaluated experimentally under different conditions of noise, asynchronous interference, sea clutters, and rain clutters. High probability of detection is achieved by designing the Constant False Alarm Rate (CFAR) processor which is the first stage in the proposed ABI for relatively high probability of false alarm. The final probability of false alarm is then reduced by the effect of integration.