Title :
Synchronous to Asynchronous Conversion of Digital Circuits
Author :
Cassia, Ricardo ; Franca, Felipe ; Alves, Vladimir
Author_Institution :
COPPE/PEE, Fed. Univ. of Rio de Janeiro
Abstract :
In this work an automated conversion method of synchronous circuits into asynchronous ones is presented. The technique utilizes the synchronous circuit fully synthesized netlist, and employs ASERT - asynchronous scheduling by edge reversal timing - for signaling and synchronization between asynchronous functional units, which are extracted from the functional blocks hierarchical organization conceived by the original synchronous circuit designer. The method utilizes CAD tools and standard cells libraries for traditional synchronous circuits in addition to specific developed software
Keywords :
asynchronous circuits; circuit CAD; logic CAD; CAD tools; asynchronous scheduling; automated conversion; digital circuits; edge reversal timing; fully synthesized netlist; standard cells libraries; synchronous circuits; synchronous-asynchronous conversion; Circuit synthesis; Design automation; Digital circuits; Scheduling; Signal design; Signal synthesis; Software libraries; Software standards; Standards development; Timing;
Conference_Titel :
Research in Microelectronics and Electronics 2006, Ph. D.
Conference_Location :
Otranto
Print_ISBN :
1-4244-0157-7
DOI :
10.1109/RME.2006.1689971
