A Low Power 128-pt Implementation of FFT/IFFT for High Performance Wireless Personal Area Networks

An architecture for low power 128-pt FFT/IFFT processor for application in IEEE 802.15.3a standard design is proposed, where the 128-pt FFT is devolved into 8-pt and 16-pt FFTs and then once again by devolving the 16-pt FFT into 4times4 and 2times8. The analysis demonstrated that with modest increase in area one can achieve significant reduction in power. The proposed architectures complete one parallel-to-parallel (i.e., when all input data are available in parallel and all output data are generated in parallel) 128-pt FFT computation in 312ns. The relative merits and demerits of these architectures have been analyzed from the algorithm as well as implementation point of view. Detailed power analysis of architecture at block level is described. From power perspective the second architecture is better; however both the architectures give significant reduction of algorithmic complexity compared to the existing schemes. For the second architecture the core power consumption is only 72mW. Apart from the low power consumption, the advantages of the proposed architecture include reduced hardware complexity, regular data flow and simple counter based control