DocumentCode :
2493029
Title :
Pile Up Rejection and Multiple Simultaneous Events Acquisition with the PDD ASIC
Author :
Dragone, A. ; De Geronimo, G. ; Fried, J. ; Kandasamy, A. ; O´Connor, P. ; Siddons, D.P. ; Vernon, E. ; Corsi, F.
Author_Institution :
Instrum. Div., Brookhaven Nat. Lab., Upton, NY
fYear :
0
fDate :
0-0 0
Firstpage :
381
Lastpage :
384
Abstract :
The peak detector derandomizer ASIC provides threshold discrimination, arbitration, peak and timing detection with analog memorization, sparsification, and multiplexation for 32 input channels of analog pulse data. In this work the ASIC, a new version of the ASIC, that can process multiple events occurring at the same time and can provide time-over-threshold measurement for pile up rejection, is presented
Keywords :
CMOS integrated circuits; application specific integrated circuits; PDD ASIC; analog memorization; analog multiplexation; analog sparsification; arbitration detection; peak detection; peak detector derandomizer; pile up rejection; simultaneous events acquisition; threshold discrimination; time-over-threshold measurement; timing detection; Application specific integrated circuits; CMOS technology; Charge measurement; Current measurement; Instruments; Laboratories; Logic; Radiation detectors; Time measurement; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Research in Microelectronics and Electronics 2006, Ph. D.
Conference_Location :
Otranto
Print_ISBN :
1-4244-0157-7
Type :
conf
DOI :
10.1109/RME.2006.1689975
Filename :
1689975
Link To Document :
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