A Hardware IP-Core for Information Retrieval

Author

Freeman, Michael ; Jayasooriya, Thimal

Author_Institution

Dept. of Comput. Sci., York Univ.

fYear

0

fDate

0-0 0

Firstpage

115

Lastpage

122

Abstract

With the ever increasing amounts of information stored on the Web or archived within computing systems, high performance data processing architectures are required to process this data in real time. The aim of the work presented in this paper is the development of a hardware text mining IP-Core for use in FPGA based systems. In this paper we describe the development of our text processing hardware pipeline, with the addition of a complex word stemming and loadable stop list stages. The performance of this system is then compared to our initial prototype and an equivalent software implementation using the Lucene software library

Keywords

data mining; field programmable gate arrays; information retrieval; software libraries; text analysis; FPGA based system; Lucene software library; hardware IP-core architecture; high performance data processing architecture; information retrieval; software implementation; text mining; text processing hardware pipeline; word stemming; Computer architecture; Data processing; Field programmable gate arrays; Hardware; High performance computing; Information retrieval; Real time systems; Service oriented architecture; Text mining; Text processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital System Design: Architectures, Methods and Tools, 2006. DSD 2006. 9th EUROMICRO Conference on

Conference_Location

Dubrovnik

Print_ISBN

0-7695-2609-8

Type

conf

DOI

10.1109/DSD.2006.8

Filename

1690028