Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart

Nowadays, synchronous processor designers have to deal with severe problems related to the distribution of a complex clock network like skew reduction, high power-consumption, synchronization of clocks, etc. Asynchronous or self-timed architectures are becoming an interesting design alternative because they usually avoid these drawbacks, and they are able to achieve high performance at a low power consumption cost. However, on the first steps of the design process, the evaluation of the performance of such architectures through simulations is much more complicated due to the requirement of modeling the data-dependant timing of each system module. The aim of this paper is to evaluate the performance of a 64-bit fully-asynchronous superscalar processor microarchitecture with dynamically scheduled instruction flow, out-of-order speculative execution of instructions and advanced branch prediction. To tackle this goal we have described the asynchronous microarchitecture solving the synchronization between structures through a four-phase handshake protocol. Then, we have used a modification of the SimpleScalar suite to model the asynchronous microarchitecture in order to run Alpha programs on it. Finally, we have compared the performance of this fully-asynchronous processor with the performance obtained from its synchronous counterpart by running architectural simulations of the SPEC2000 benchmarks on both models