Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes

Author

Galke, C. ; Gätzschmann, U. ; Vierhaus, H.T.

Author_Institution

Brandenburg Univ. of Technol., Cottbus

fYear

0

fDate

0-0 0

Firstpage

433

Lastpage

438

Abstract

The ever-increasing complexity of systems on a chip (SoCs) has driven scan-based logic test technologies to their limits. Built-in self-test is one possible solution to overcome the problem. However, externally controlled test procedures that allow the re-use of existing testers and adaption to changing patterns seem to gain a higher level of industrial acceptance. Then a high degree of test pattern compaction without sacrificing test coverage is essential. This paper describes a versatile pattern compaction scheme that is independent from special ATPG tools, can be optimized for either hard-to-test versus large circuits and can even accommodate bit settings in LFSR outputs

Keywords

built-in self test; circuit complexity; logic testing; system-on-chip; built-in self-test; scan-based SoC test; space-time pattern compaction schemes; systems on a chip complexity; Automatic test pattern generation; Circuit testing; Compaction; Costs; Logic testing; Space technology; System testing; System-on-a-chip; Test equipment; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital System Design: Architectures, Methods and Tools, 2006. DSD 2006. 9th EUROMICRO Conference on

Conference_Location

Dubrovnik

Print_ISBN

0-7695-2609-8

Type

conf

DOI

10.1109/DSD.2006.83

Filename

1690070