A RISC Processor with Redundant LNS Instructions

Author

Arnold, Mark G.

Author_Institution

Lehigh Univ., Bethlehem, PA

fYear

0

fDate

0-0 0

Firstpage

475

Lastpage

482

Abstract

This paper presents Verilog code and FPGA synthesis results for a 32-bit RISC processor (RAWE) that uses the dual redundant logarithmic number system (DRLNS). A benchmark shows pure-software logarithmic arithmetic can be faster than floating point in some applications. An earlier processor (AWE) doubles that speed using hardware support for unsigned LNS values. In this the modest additional hardware allows the proposed RAWE to do signed multiply accumulate two to three times faster than AWE

Keywords

field programmable gate arrays; hardware description languages; reduced instruction set computing; redundant number systems; 32-bit RISC processor; FPGA synthesis; Verilog code; dual redundant logarithmic number system instructions; field programmable gate arrays; hardware support; reduced instruction set computing; software logarithmic arithmetic; unsigned logarithmic number system values; Acceleration; Application software; Clocks; Cloning; Costs; Field programmable gate arrays; Floating-point arithmetic; Hardware design languages; Microprocessors; Reduced instruction set computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital System Design: Architectures, Methods and Tools, 2006. DSD 2006. 9th EUROMICRO Conference on

Conference_Location

Dubrovnik

Print_ISBN

0-7695-2609-8

Type

conf

DOI

10.1109/DSD.2006.15

Filename

1690076