Title :
State Assignment for Detecting Erroneous Transitions in Finite State Machines
Author_Institution :
Inst. fur Informatik, Frankfurt Univ.
Abstract :
A new concurrent error detection scheme for detecting faulty transitions in finite state machines is presented. Instead of assigning codewords to states, codewords are assigned to transitions by an appropriate state assignment. For the detection of one erroneous bit, it is possible in certain cases to find such an assignment without adding extra state bits. The resulting area overhead is determined for some benchmark examples. Finally, a system paradigm is sketched which uses error detection for soft error correction and reliability management
Keywords :
error correction codes; error detection codes; finite state machines; logic design; state assignment; concurrent error detection scheme; erroneous transition detection; faulty transition detection; finite state machines; reliability management; soft error correction; state assignment; Automata; Circuit faults; Clocks; Digital systems; Error correction; Fault detection; Law; Legal factors; Logic; Sequential circuits;
Conference_Titel :
Digital System Design: Architectures, Methods and Tools, 2006. DSD 2006. 9th EUROMICRO Conference on
Conference_Location :
Dubrovnik
Print_ISBN :
0-7695-2609-8
DOI :
10.1109/DSD.2006.85
