Title :
Memory Generation and Power Distribution In SOC
Author_Institution :
SanDisk Corporation, USA
Abstract :
This paper describes the on-chip SRAMs design flow in one SOC chip. We show a model to estimate the coupling noise in the existence of power rings around SRAMs. SRAM blocks usually use the lower level metals and the top metals over the SRAM could be used for power distribution and global signals. Power noise has the global impact on SRAMs and chip performance. We discuss the full chip power grid planning methodology, including power rings and power strap lines over SRAM blocks, in order to meet the power noise budget
Keywords :
SRAM chips; logic design; system-on-chip; SOC chip; memory generation; on-chip SRAM design flow; power distribution; power grid planning methodology; system-on-chip; Coupling circuits; Digital signal processing chips; Fabrics; Noise cancellation; Power distribution; Power generation; Power grids; Power system planning; Random access memory; System-on-a-chip;
Conference_Titel :
Digital System Design: Architectures, Methods and Tools, 2006. DSD 2006. 9th EUROMICRO Conference on
Conference_Location :
Dubrovnik
Print_ISBN :
0-7695-2609-8
DOI :
10.1109/DSD.2006.66
