DocumentCode :
2494961
Title :
Two Architectures of a General Digit-Serial Normal Basis Multiplier
Author :
Novotny, Martin ; Schmidt, Jan
Author_Institution :
Dept. of Comput. Sci. & Eng., Czech Tech. Univ., Praha
fYear :
0
fDate :
0-0 0
Firstpage :
550
Lastpage :
553
Abstract :
We present two architectures of digit-serial normal basis multiplier over GF(2m). Proposed multipliers are scalable by the digit width of general value in difference of the multiplier of Agnew et al., that may be scaled only by digit width that divides the degree m. This helps designers to trade area for speed e.g. in cryptographic systems, where m should be a prime number. Functionality of multipliers has been tested by simulation and implemented in Xilinx Virtex 4 FPGA
Keywords :
Galois fields; cryptography; digital arithmetic; number theory; Xilinx Virtex 4 FPGA; cryptographic systems; digit-serial normal basis multiplier; prime number; Arithmetic; Clocks; Computer architecture; Computer science; Cryptography; Field programmable gate arrays; Galois fields; Logic; Polynomials; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Digital System Design: Architectures, Methods and Tools, 2006. DSD 2006. 9th EUROMICRO Conference on
Conference_Location :
Dubrovnik
Print_ISBN :
0-7695-2609-8
Type :
conf
DOI :
10.1109/DSD.2006.91
Filename :
1690086
Link To Document :
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