A High Level Power Model for the Nostrum NoC

Author

Penolazzi, Sandro ; Jantsch, Axel

Author_Institution

Royal Inst. of Technol., Kista

fYear

0

fDate

0-0 0

Firstpage

673

Lastpage

676

Abstract

We propose a power model for the Nostrum NoC. For this purpose an empirical power model of links and switches has been formulated and validated with the synopsys power compiler. The model, which from now on will be called Nos-HPM (Nostrum high-level power model) allows a fast power analysis and is accurate within 5%. System simulations with Nos-HPM run up to 500 times faster than with power compiler for a 4 times 4 network. We find a maximum power consumption of 0.7 W for a 4 times 4 mesh and 3.5 W for an 8 times 8 mesh, both implemented in 0.18mum UPC CMOS technology. In the worst case the average energy per cycle for a 128-bit packet is 508 pJ, while it is 20 pJ for a payload byte. The power consumption of all the links is equivalent or slightly higher than the power consumption of all the switches. A comparison between our results and some related work is also presented

Keywords

circuit simulation; network-on-chip; power aware computing; program compilers; Nos-HPM; Nostrum NoC; UPC CMOS technology; empirical power model; power consumption; synopsys power compiler; CMOS technology; Energy consumption; Network interfaces; Network-on-a-chip; Payloads; Power system modeling; Spine; Switches; Virtual colonoscopy; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital System Design: Architectures, Methods and Tools, 2006. DSD 2006. 9th EUROMICRO Conference on

Conference_Location

Dubrovnik

Print_ISBN

0-7695-2609-8

Type

conf

DOI

10.1109/DSD.2006.9

Filename

1690102