• DocumentCode
    2495324
  • Title

    Multi-Gbps FPGA-Based Low Density Parity Check (LDPC) Decoder Design

  • Author

    Zarubica, R. ; Wilson, Stephen G. ; Hall, Eric

  • Author_Institution
    Univ. of Virginia, Charlottesville
  • fYear
    2007
  • fDate
    26-30 Nov. 2007
  • Firstpage
    548
  • Lastpage
    552
  • Abstract
    A novel high-throughput (6 Gb/s), fully-parallel FPGA-based 1200-bit rate-1/2 Low Density Parity Check (LDPC) decoder design is presented. The decoder features a PEG- based regular (6,3) code and a modified min-sum algorithm that improves performance without any additional hardware overhead.
  • Keywords
    decoding; field programmable gate arrays; parity check codes; FPGA; LDPC decoder design; low density parity check; Cities and towns; Code standards; Communication standards; Digital video broadcasting; Field programmable gate arrays; Hardware; Iterative decoding; Message passing; Parity check codes; Sparse matrices;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Global Telecommunications Conference, 2007. GLOBECOM '07. IEEE
  • Conference_Location
    Washington, DC
  • Print_ISBN
    978-1-4244-1042-2
  • Electronic_ISBN
    978-1-4244-1043-9
  • Type

    conf

  • DOI
    10.1109/GLOCOM.2007.108
  • Filename
    4411018
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2495324