3D-SiP: The latest miniaturization technology

Author

Schaper, Leonard W.

Author_Institution

Univ. of Arkansas, Fayetteville, AR

fYear

2008

fDate

1-2 Dec. 2008

Firstpage

3

Lastpage

6

Abstract

The latest packaging trend of three dimensional system in package (3D-SiP), based either on direct 3D silicon IC stacking or on the use of silicon or organic interposers, is placed in the context of the historical trend toward smaller, faster, and cheaper electronic systems. It can be shown that virtually all packaging advances have been directed toward the reduction of total system interconnect length, and the reduction of superfluous material not required to perform electronic functions. Examples are presented from the days of vacuum tube systems to the present 3D silicon approaches. Various technologies being developed for 3D-SiP are described. Though these approaches differ in technical details, they are all attempting to continue the 50+ year tread of electronics miniaturization through reducing material volume and interconnect length.

Keywords

semiconductor materials; silicon; system-in-package; 3D silicon IC stacking; 3D-SiP; electronics miniaturization; organic interposers; three dimensional system in package; total system interconnect length reduction; Analog integrated circuits; Costs; Digital systems; Electron tubes; Electronics packaging; Integrated circuit interconnections; Integrated circuit packaging; Silicon; Transformers; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Packaging Workshop of Japan, 2008. VPWJ 2008. IEEE 9th

Conference_Location

Kyoto

Print_ISBN

978-1-4244-3498-5

Type

conf

DOI

10.1109/VPWJ.2008.4762187

Filename

4762187