Title :
BIST diagnostics. I. Simulation models
Author_Institution :
Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
Abstract :
An efficient method is described for using fault simulation as a solution to the diagnostic problem created by the presence of embedded memories in BIST designs. The idea is to create simulation models that only use combinational logic (i.e., the memory is removed)
Keywords :
built-in self test; embedded systems; fault diagnosis; logic simulation; logic testing; BIST diagnostics; combinational logic; embedded memories; fault simulation; simulation models; Built-in self-test; Circuit faults; Circuit testing; Clocks; Fault diagnosis; Hardware; Logic design; Logic testing; Random access memory; Shift registers;
Conference_Titel :
Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian
Print_ISBN :
0-8186-8277-9
DOI :
10.1109/ATS.1998.741569
