• DocumentCode
    2495821
  • Title

    BIST diagnostics. I. Simulation models

  • Author

    Savir, Jacob

  • Author_Institution
    Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
  • fYear
    1998
  • fDate
    2-4 Dec 1998
  • Firstpage
    8
  • Lastpage
    14
  • Abstract
    An efficient method is described for using fault simulation as a solution to the diagnostic problem created by the presence of embedded memories in BIST designs. The idea is to create simulation models that only use combinational logic (i.e., the memory is removed)
  • Keywords
    built-in self test; embedded systems; fault diagnosis; logic simulation; logic testing; BIST diagnostics; combinational logic; embedded memories; fault simulation; simulation models; Built-in self-test; Circuit faults; Circuit testing; Clocks; Fault diagnosis; Hardware; Logic design; Logic testing; Random access memory; Shift registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian
  • ISSN
    1081-7735
  • Print_ISBN
    0-8186-8277-9
  • Type

    conf

  • DOI
    10.1109/ATS.1998.741569
  • Filename
    741569
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2495821