DocumentCode :
2495915
Title :
Enabling Dynamic Voltage & Frequency Scaling in next-generation microprocessors: Thermal & reliability considerations
Author :
Ankireddi, Sai ; Copeland, David
Author_Institution :
Sun Microsyst. Inc., Santa Clara, CA
fYear :
2008
fDate :
1-2 Dec. 2008
Firstpage :
35
Lastpage :
38
Abstract :
With each advancing generation of process technology, the CPU power continues to rise, creating additional issues for thermal/mechanical packaging design. A common therme in next-generation CPU offerings will be the use of dynamic voltage and frequency. Scaling (DVFS) to manage the chip power during operation. With a DVFS policy, it becomes all the more important to study the potential impacts of imposed temporal variation in power on the thermo-mechanical reliability. In this study, we demonstrate a system identification approach for a practical CPU application and exemplify the trade-offs involved in creating a DVFS policy that is satisfactory to both thermal/mechanical reliability engineers and CPU design teams.
Keywords :
microprocessor chips; packaging; reliability; CPU; chip power; dynamic voltage; frequency scaling; mechanical packaging; microprocessors; thermal packaging; thermomechanical reliability; Dynamic voltage scaling; Energy management; Frequency; Microprocessors; Packaging; Power generation; Power system management; Power system reliability; System identification; Thermomechanical processes;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Packaging Workshop of Japan, 2008. VPWJ 2008. IEEE 9th
Conference_Location :
Kyoto
Print_ISBN :
978-1-4244-3498-5
Type :
conf
DOI :
10.1109/VPWJ.2008.4762198
Filename :
4762198
Link To Document :
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