Title :
Test cycle count reduction in a parallel scan BIST environment
Author :
Ayari, Bechir ; Varma, Prab
Abstract :
This paper describes a novel method that can be used to reduce test cycle count in a parallel access scan based built-in-self-test (BIST) environment. An algorithm that allows the efficient application of deterministically generated patterns is proposed. This approach allows BIST fault coverage to be increased using deterministic vectors, while minimizing the cost, in terms of test cycles, of applying the vectors
Keywords :
automatic test pattern generation; boundary scan testing; built-in self test; fault diagnosis; deterministic vectors; deterministically generated patterns; fault coverage; parallel access; parallel scan BIST environment; test cycle count reduction; test cycles; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Clocks; Costs; Linear feedback shift registers; Test pattern generators; Vectors;
Conference_Titel :
Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian
Print_ISBN :
0-8186-8277-9
DOI :
10.1109/ATS.1998.741573
