DocumentCode
2496123
Title
Alleviating DFT cost using testability driven HLS
Author
Flottes, M.L. ; Pires, R. ; Rouzeyre, B.
Author_Institution
Lab. d´´Inf., CNRS, Montpellier, France
fYear
1998
fDate
2-4 Dec 1998
Firstpage
46
Lastpage
51
Abstract
This paper presents a method to carry out the register allocation phase of high level synthesis with testability considerations. Testability problems are identified and eliminated during this step turning testability/area trade-off to account. It allows one to decrease the cost related to the application of low-level DFT techniques
Keywords
automatic testing; design for testability; high level synthesis; DFT cost; area trade-off; high level synthesis; low-level DFT techniques; register allocation phase; step turning; testability driven HLS; Circuit synthesis; Circuit testing; Costs; Degradation; Flow graphs; High level synthesis; Reactive power; Registers; Resource management; Robots; Turning;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian
ISSN
1081-7735
Print_ISBN
0-8186-8277-9
Type
conf
DOI
10.1109/ATS.1998.741582
Filename
741582
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